Logic Optimization Techniques for Multiplexers

This paper explores how synthesis tools such as Mentor Graphics’ Precision RTL Synthesis can infer different types of multiplexers from different styles of HDL code, and how these structures can be mapped into FPGA devices. Inefficient multiplexers can greatly increase the logic required to implement your design. This paper discusses some common pitfalls and provides design guidelines to achieve optimal resource utilization for multiplexer designs in 4-input look-up table (LUT) based architectures such as Altera’s Stratix device family.